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本帖最后由 xinxincaijq 于 2013-1-9 10:27 编辑
一步一步学ZedBoard & Zynq(四)：基于AXI Lite 总线的从设备IP设计 转自博客：http://www.eeboard.com/bbs/thread-6206-1-1.html 本小节通过使用XPS中的定制IP向导(ipwiz)，为已经存在的ARM PS 系统添加用户自定IP(Custom IP )，了解AXI Lite IP基本结构，并掌握AXI Lite IP的定制方法，为后续编写复杂AXI IP打下基础。同时本小节IP定制方法同样适用于MicroBlaze处理系统。 本小节定制的是简单LED的IP，只有一个数据寄存器，向其写值就可以控制8个LED相应亮灭。 更多更新请关注我的博客：@超群天晴 http://www.cnblogs.com/surpassal/ 硬件平台：Digilent ZedBoard 开发环境：Windows XP 32 bit 软件： XPS 14.2 +SDK 14.2 一、创建ARM PS系统 同前面几节一样，首先使用XPS创建ARM PS系统。需要注意的是，在选择外设时，同样不要添加任何外设
二、定制AXI IP ARM PS系统创建结束后，就可以开始定制用户自定义IP。XPS提供了Create or Import Peripheral Wizward 向导，使得用户自定义IP的创建变得非常简单。当然在熟悉了AXI IP核结构和代码编写规则后，可以直接编写自己的IP核而不使用向导。这里采用向导方式。 1、产生AXI IP外设模版 Hardware->Create or Import Peripheral Wizward ，启动向导
欢迎界面
选择从模板创建新外设
默认是将外设直接包含到当前XPS工程中
填入外设名。注意必须都是小写。这里我们建立的是my_axi_ip。下面是版本控制，可以根据需要修改。同时面板的最下方还提示了将创建名为my_axi_ip_v1_00_a的库(其实就是一个目录)，所有实现这个IP的HDL文件都在这个库中。 接下来要选择外设总线的类型。AXI4_Lite为最基本的AXI 总线，用于简单处理，所有空间访问都是通过地址/寄存器方式访问，不支持突发；AXI4是标准AXI4总线标准，支持突然，支持高速；AXI4_Stream专门为数据流而设计。
在IPIF (IP 接口) 配置，这里配置接口的一些属性，如是否是AXI 主/从设备等。我们所定制的IP是一个从设备，因而不需要使用主设备接口。
选择需啊哟的寄存器数量。因为我们只需要一个数据寄存器，这里选1。
接下来就是IPIC(IP 互联)，也就是IP的接口信号。以BUS2开头的信号，意味对IP来说，这些信号是输入信号；同样IP2BUS意味着输出信号。 这里一些信号做一些说明。
BUS2IP_WrCE（Write Chip Enable，写使能）
writable registers selection. 复制代码 BUS2IP_Data（Write Data，写数据）
复制代码 BUS2IP_BE（Byte Enable，字节使能）
valid data. 复制代码 IPBUS2_RdAck（Read Acknowledgement，读反馈）
复制代码 接下来需要使用需要使用BFM (Bus Functional Models， 总线功能模型)对外设进行仿真。本例IP很简单，不要使用。
最后，需要选择HDL类型、ISE工程支持和软件驱动模板。因为我比较习惯使用verilog，因而使用verilog模板。需要说明的是，IP接口仍然是VHDL编写，只是用户逻辑改用verilog。如果不需要使用软件驱动模板的话，可以不选上。这里选上了，但是后续编程的时候我并没有用。
最后给出了外设的信息summary。支持，my_axi_ip"外壳"基本完成。后续我们只需要对user_logic进行编写，并修改元件引脚即可。
2、编写IP 修改.mpd文件，在目录 Lab4\pcores\my_axi_ip_v1_00_a\data\
## ## Name : my_axi_ip ## Desc : Microprocessor Peripheral Description ## : Automatically generated by PsfUtility ## ################################################################### BEGIN my_axi_ip ## Peripheral Options OPTION IPTYPE = PERIPHERAL OPTION IMP_NETLIST = TRUE OPTION HDL = MIXED OPTION IP_GROUP = MICROBLAZE:USER OPTION DESC = MY_AXI_IP OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT) ## Bus Interfaces BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE ## Generics for VHDL or Parameters for Verilog PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI PARAMETER C_USE_WSTRB = 0, DT = INTEGER PARAMETER C_DPHASE_TIMEOUT = 8, DT = INTEGER PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI PARAMETER C_FAMILY = virtex6, DT = STRING PARAMETER C_NUM_REG = 1, DT = INTEGER PARAMETER C_NUM_MEM = 1, DT = INTEGER PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI ## Ports PORT LED = "", DIR = O, VEC = [7:0] PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI END 复制代码 其中，第39行
复制代码 是我们添加上的，表明我们为其添加了一个名为LED的端口，方向是输出，长度是8位。其他行代码为默认，不需要修改。 修改用户逻辑，在 Lab4\pcores\my_axi_ip_v1_00_a\hdl\verilog\user_logic.v
// user_logic.v - module //---------------------------------------------------------------------------- // // *************************************************************************** // ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** // ** ** // ** Xilinx, Inc. ** // ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** // ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** // ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** // ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** // ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** // ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** // ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** // ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** // ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** // ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** // ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** // ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** // ** FOR A PARTICULAR PURPOSE. ** // ** ** // *************************************************************************** // //---------------------------------------------------------------------------- // Filename: user_logic.v // Version: 1.00.a // Description: User logic module. // Date: Tue Oct 09 18:28:06 2012 (by Create and Import Peripheral Wizard) // Verilog Standard: Verilog-2001 //---------------------------------------------------------------------------- // Naming Conventions: // active low signals: "*_n" // clock signals: "clk", "clk_div#", "clk_#x" // reset signals: "rst", "rst_n" // generics: "C_*" // user defined types: "*_TYPE" // state machine next state: "*_ns" // state machine current state: "*_cs" // combinatorial signals: "*_com" // pipelined or register delay signals: "*_d#" // counter signals: "*cnt*" // clock enable signals: "*_ce" // internal version of output port: "*_i" // device pins: "*_pin" // ports: "- Names begin with Uppercase" // processes: "*_PROCESS" // component instantiations: "<ENTITY_>I_<#|FUNC>" //---------------------------------------------------------------------------- `uselib lib=unisims_ver `uselib lib=proc_common_v3_00_a module user_logic ( // -- ADD USER PORTS BELOW THIS LINE --------------- LED, // -- ADD USER PORTS ABOVE THIS LINE --------------- // -- DO NOT EDIT BELOW THIS LINE ------------------ // -- Bus protocol ports, do not add to or delete Bus2IP_Clk, // Bus to IP clock Bus2IP_Resetn, // Bus to IP reset Bus2IP_Data, // Bus to IP data bus Bus2IP_BE, // Bus to IP byte enables Bus2IP_RdCE, // Bus to IP read chip enable Bus2IP_WrCE, // Bus to IP write chip enable IP2Bus_Data, // IP to Bus data bus IP2Bus_RdAck, // IP to Bus read transfer acknowledgement IP2Bus_WrAck, // IP to Bus write transfer acknowledgement IP2Bus_Error // IP to Bus error response // -- DO NOT EDIT ABOVE THIS LINE ------------------ ); // user_logic // -- ADD USER PARAMETERS BELOW THIS LINE ------------ // --USER parameters added here // -- ADD USER PARAMETERS ABOVE THIS LINE ------------ // -- DO NOT EDIT BELOW THIS LINE -------------------- // -- Bus protocol parameters, do not add to or delete parameter C_NUM_REG = 1; parameter C_SLV_DWIDTH = 32; // -- DO NOT EDIT ABOVE THIS LINE -------------------- // -- ADD USER PORTS BELOW THIS LINE ----------------- output [7:0] LED; // -- ADD USER PORTS ABOVE THIS LINE ----------------- // -- DO NOT EDIT BELOW THIS LINE -------------------- // -- Bus protocol ports, do not add to or delete input Bus2IP_Clk; input Bus2IP_Resetn; input [C_SLV_DWIDTH-1 : 0] Bus2IP_Data; input [C_SLV_DWIDTH/8-1 : 0] Bus2IP_BE; input [C_NUM_REG-1 : 0] Bus2IP_RdCE; input [C_NUM_REG-1 : 0] Bus2IP_WrCE; output [C_SLV_DWIDTH-1 : 0] IP2Bus_Data; output IP2Bus_RdAck; output IP2Bus_WrAck; output IP2Bus_Error; // -- DO NOT EDIT ABOVE THIS LINE -------------------- //---------------------------------------------------------------------------- // Implementation //---------------------------------------------------------------------------- // --USER nets declarations added here, as needed for user logic // Nets for user logic slave model s/w accessible register example reg [C_SLV_DWIDTH-1 : 0] slv_reg0; wire [0 : 0] slv_reg_write_sel; wire [0 : 0] slv_reg_read_sel; reg [C_SLV_DWIDTH-1 : 0] slv_ip2bus_data; wire slv_read_ack; wire slv_write_ack; integer byte_index, bit_index; // USER logic implementation added here assign LED = slv_reg0[7:0]; // ------------------------------------------------------ // Example code to read/write user logic slave model s/w accessible registers // // Note: // The example code presented here is to show you one way of reading/writing // software accessible registers implemented in the user logic slave model. // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond // to one software accessible register by the top level template. For example, // if you have four 32 bit software accessible registers in the user logic, // you are basically operating on the following memory mapped registers: // // Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register // "1000" C_BASEADDR + 0x0 // "0100" C_BASEADDR + 0x4 // "0010" C_BASEADDR + 0x8 // "0001" C_BASEADDR + 0xC // // ------------------------------------------------------ assign slv_reg_write_sel = Bus2IP_WrCE[0:0], slv_reg_read_sel = Bus2IP_RdCE[0:0], slv_write_ack = Bus2IP_WrCE[0], slv_read_ack = Bus2IP_RdCE[0]; // implement slave model register(s) always @( posedge Bus2IP_Clk ) begin if ( Bus2IP_Resetn == 1'b0 ) begin slv_reg0 <= 0; end else case ( slv_reg_write_sel ) 1'b1 : for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 ) if ( Bus2IP_BE[byte_index] == 1 ) slv_reg0[(byte_index*8) +: 8] <= Bus2IP_Data[(byte_index*8) +: 8]; default : begin slv_reg0 <= slv_reg0; end endcase end // SLAVE_REG_WRITE_PROC // implement slave model register read mux always @( slv_reg_read_sel or slv_reg0 ) begin case ( slv_reg_read_sel ) 1'b1 : slv_ip2bus_data <= slv_reg0; default : slv_ip2bus_data <= 0; endcase end // SLAVE_REG_READ_PROC // ------------------------------------------------------------ // Example code to drive IP to Bus signals // ------------------------------------------------------------ assign IP2Bus_Data = (slv_read_ack == 1'b1) ? slv_ip2bus_data : 0 ; assign IP2Bus_WrAck = slv_write_ack; assign IP2Bus_RdAck = slv_read_ack; assign IP2Bus_Error = 0; endmodule 复制代码 代码中57、86行
output [7:0] LED; 复制代码 表明在用户逻辑中，定义了名为LED的端口，方向是输出，长度为8。 代码中119行
复制代码 表明将slv_reg0的低8位传递给输出端口LED。其实就是实现了数据寄存器的值作用到输出端口的功能。 需要将用户逻辑和IPIF连接上，需要完成user_logic的例化 Lab4\pcores\my_axi_ip_v1_00_a\hdl\vhdl\my_axi_ip.vhd
-- my_axi_ip.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: my_axi_ip.vhd -- Version: 1.00.a -- Description: Top level design, instantiates library components and user logic. -- Date: Tue Oct 09 18:28:06 2012 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width -- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width -- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size -- C_USE_WSTRB -- AXI4LITE slave: Write Strobe -- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout -- C_BASEADDR -- AXI4LITE slave: base address -- C_HIGHADDR -- AXI4LITE slave: high address -- C_FAMILY -- FPGA Family -- C_NUM_REG -- Number of software accessible registers -- C_NUM_MEM -- Number of address-ranges -- C_SLV_AWIDTH -- Slave interface address bus width -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- S_AXI_ACLK -- AXI4LITE slave: Clock -- S_AXI_ARESETN -- AXI4LITE slave: Reset -- S_AXI_AWADDR -- AXI4LITE slave: Write address -- S_AXI_AWVALID -- AXI4LITE slave: Write address valid -- S_AXI_WDATA -- AXI4LITE slave: Write data -- S_AXI_WSTRB -- AXI4LITE slave: Write strobe -- S_AXI_WVALID -- AXI4LITE slave: Write data valid -- S_AXI_BREADY -- AXI4LITE slave: Response ready -- S_AXI_ARADDR -- AXI4LITE slave: Read address -- S_AXI_ARVALID -- AXI4LITE slave: Read address valid -- S_AXI_RREADY -- AXI4LITE slave: Read data ready -- S_AXI_ARREADY -- AXI4LITE slave: read addres ready -- S_AXI_RDATA -- AXI4LITE slave: Read data -- S_AXI_RRESP -- AXI4LITE slave: Read data response -- S_AXI_RVALID -- AXI4LITE slave: Read data valid -- S_AXI_WREADY -- AXI4LITE slave: Write data ready -- S_AXI_BRESP -- AXI4LITE slave: Response -- S_AXI_BVALID -- AXI4LITE slave: Resonse valid -- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready ------------------------------------------------------------------------------ entity my_axi_ip is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer := 8; C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_NUM_REG : integer := 1; C_NUM_MEM : integer := 1; C_SLV_AWIDTH : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ LED : out std_logic_vector(7 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute SIGIS of S_AXI_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; end entity my_axi_ip; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of my_axi_ip is constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); constant USER_SLV_NUM_REG : integer := 1; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant TOTAL_IPIF_CE : integer := USER_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Resetn : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; ------------------------------------------ -- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 1; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ LED : out std_logic_vector(7 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE, Bus2IP_Data => ipif_Bus2IP_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, IP2Bus_Data => ipif_IP2Bus_Data ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => USER_SLV_DWIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ LED => LED, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); end IMP; 复制代码 137行
复制代码 定义IP的端口为LED，这里需要和之前修改MPD文件一致。 232-268行为元件声明
-- Component declaration for verilog user logic ------------------------------------------ component user_logic is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- --USER generics added here -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_NUM_REG : integer := 1; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ LED : out std_logic_vector(7 downto 0); -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete Bus2IP_Clk : in std_logic; Bus2IP_Resetn : in std_logic; Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0); Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0); Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0); Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0); IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0); IP2Bus_RdAck : out std_logic; IP2Bus_WrAck : out std_logic; IP2Bus_Error : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); end component user_logic; 复制代码 323-352行为user_logic元件例化。VHDL是不区分大小写的。
-- instantiate User Logic ------------------------------------------ USER_LOGIC_I : component user_logic generic map ( -- MAP USER GENERICS BELOW THIS LINE --------------- --USER generics mapped here -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => USER_SLV_DWIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ LED => LED, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); 复制代码 这几个文件修改后保存。 Project->Rescan User Repositories（更新用户仓库？），让XPS识别到对IP所做的修改
三、将自定义IP核添加到PS系统 同第三篇一样，需要将IP添加到PS系统中。 在Ports标签中，需要将我们定义的LED端口设置为外部端口，外部引脚名按照Zedboard的习惯，定义为LD
在Address标签中，设定IP的地址。XPS支持自定义定制范围、空间大小等。可以使用默认设置，也可以手动设置。这里我设置基地址为0x40000000，其实也就是我们设定的数据寄存器的地址为0x40000000。如果有更多的寄存器，会以4字节offset 地址的方式访问即可。
最后一样修改ucf文件，完成约束。
NET LD[1] LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1" NET LD[2] LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2" NET LD[3] LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3" NET LD[4] LOC = V22 | IOSTANDARD=LVCMOS33; # "LD4" NET LD[5] LOC = W22 | IOSTANDARD=LVCMOS33; # "LD5" NET LD[6] LOC = U19 | IOSTANDARD=LVCMOS33; # "LD6" NET LD[7] LOC = U14 | IOSTANDARD=LVCMOS33; # "LD7" 复制代码 最后对这个系统编译，生成bitstream文件，并将硬件配置导入到SDK，并启动SDK。 四、使用SDK编写IP核驱动程序和应用程序 打开SDK，可以从系统信息system.xml中看到我们的系统信息。可以看到我们实例化连接到系统的ip是my_axi_ip_0，基地址是0x4000000。
建立软件工程后，修改main代码，如下
#include <stdio.h> #include "xparameters.h" #include "xil_types.h" #include "xstatus.h" #include "xil_io.h"//包含xil_io头文件，完成对绝对地址的访问 #include "platform.h" #define LED_DATA_REG 0x40000000 void print(char *ptr); void delay(unsigned int delaytime); void LED_Play(unsigned char led); int main(void) { init_platform(); print("ZedBoard LAB4: MY_AXI_LEDs\n\r"); print("超群天晴 2012年10月8日22:12:31\n\r"); LED_Play(0x03); while(1); cleanup_platform(); return 0; } void delay(unsigned int delaytime) { int i; for(i=0;i<delaytime;i++) ; } void LED_Play(unsigned char led) { for(;;) { led=(led<<1)|(led>>7); Xil_Out32(LED_DATA_REG,led); delay(50000000); } } 复制代码 定义了两个函数
void LED_Play(unsigned char led); 复制代码 其中delay()为延时函数，参数为延时时间，100000000大约延时1s； LED_Play()为LED流水灯函数，参数是流水初始值。在程序里面设定的是0x2，也就LD0、LD1最开始亮，然后流水。 其中第8行
复制代码 使用宏定义，定义LED_DATA_REG，实际上就是自定义IP的基地址。 第44行
复制代码 使用了xil_io.h提供的绝对地址访问函数Xil_Out32(u32 OutAddress, u32 Value)，定义如下
/** * * Performs an output operation for a 32-bit memory location by writing the * specified Value to the the specified address. * * @param OutAddress contains the address to perform the output operation * at. * @param Value contains the Value to be output at the specified address. * * @return None. * * @note None. * ******************************************************************************/ void Xil_Out32(u32 OutAddress, u32 Value) { /* write the contents of the I/O location and then synchronize the I/O * such that the I/O operation completes before proceeding on */ *(volatile u32 *) OutAddress = Value; SYNCHRONIZE_IO; } 复制代码 可以看出，其实现的功能就是向32位绝对地址OutAddress中写入32位无符号值Value。参考这样的写法，可以将地址访问修改
#define LED_DATA_REG(x) *(volatile unsigned int *) LED_DATA_ADDR = x 复制代码 然后修改寄存器的值，只需要修改LED_DATA_REG(x)参数x的值即可。 四、运行结果 编译下载之后，可以从超级终端看到调试信息
同时Zedboard上的 LD 流水
================================ 备注： 有关AXI协议，请参考 AXI Bus Functional Model v1.1 Product Brief AXI Reference Guide (AXI) 更多资料，请参考 AXI IP Documentation ================================ 完整工程代码： Lab4.rar (4.73 相关阅读： 一步一步学ZedBoard & Zynq(一)：ZedBoard的第一个工程Helloworld |
